- Why in news
- On 4 January 2026, PIB published an explainer on the Design Linked Incentive (DLI) Scheme, listing its results: 24 projects sanctioned, 16 tape-outs and 6 chips fabricated.
- What it is
- The DLI Scheme is a MeitY scheme under the Semicon India Programme, launched in December 2021. It aims to build a self-reliant chip design (fabless) ecosystem. It gives startups, MSMEs and other domestic companies financial incentives, and gives startups and MSMEs access to shared design infrastructure.
- Implementing bodies
- MeitY runs the scheme. C-DAC is the nodal agency and has set up the ChipIN Centre.
- Design infrastructure
- The ChipIN Centre provides a National EDA Tool Grid, an IP core repository, MPW prototyping support and post-silicon validation support.
- Parent programme
- The Semicon India Programme has an outlay of ₹76,000 crore. It covers semiconductor and display manufacturing and the design ecosystem.
Don’t confuse with DLI vs PLI: DLI reimburses design costs and pays sales-linked incentives for chip design. PLI schemes pay incentives on incremental sales of manufactured goods.
Don’t confuse with DLI vs C2S: DLI backs companies with incentives and design tools. C2S builds chip design manpower in academic institutions.
Schemes: 52 Prelims questions since 2013, 10 in Prelims 2026 alone. They test features, the period and who funds it. In Mains, 33 news-triggered questions, mostly GS3.
Why it matters
- Design gives most of a chip's value, so the scheme helps India move up the value chain and cut import dependence.
- It supports strategic autonomy in defence, telecom and AI by building indigenous IP.
Problems
- India has no leading-edge fabs, so designs must be made at foreign foundries.
- Startups face high costs, long gestation and a shortage of experienced design talent.
Way forward
- Link design support with fab and OSAT capacity under ISM so designs reach volume production.
- Scale talent programmes and give startups long-term market access through government procurement.
Put in your answer
Indigenous processors: The Microprocessor Development Programme produced the open-source VEGA, SHAKTI and AJIT microprocessors.
- 2025Mains GS3 · Q16Challenges facing India's semiconductor industry; features of India Semiconductor Mission.
- 2025Mains GS3 · Q12Rationale, achievements, and improvements of the Production Linked Incentive scheme.
- 2026Mains GS3 · Q12Startups' role in entrepreneurship and challenges; suggested measures to overcome them.
- 2023Prelims Q88Statements on India's PLI scheme and its beneficiaries, with explanation linkage.
- 2026Prelims Q83Which semiconductor plant and location pairing is not correctly matched?
UPSC’s own questions that come close to this issue, from our Prelims and Mains banks.
Prelims practice · Statements
Ours, not from a UPSC paper
Consider the following statements:
- 1.The Design Linked Incentive (DLI) Scheme is implemented by the Ministry of Electronics and Information Technology under the Semicon India Programme.
- 2.The Indian Space Research Organisation is the nodal agency for implementing the DLI Scheme.
- 3.Under the Deployment Linked Incentive of the DLI Scheme, incentives of 6% to 4% of net sales turnover are provided for five years, subject to a cap of ₹30 crore per application.
Which of the statements given above is/are correct?
True or false?
1 of 4
Statements the way Prelims prints them. Say first, then see the fact.
1.The Design Linked Incentive Scheme is implemented by the Ministry of Electronics and Information Technology under the Semicon India Programme.
True. MeitY implements DLI under the Semicon India Programme.
2.The nodal agency for implementing the scheme is the Indian Space Research Organisation.
False. C-DAC is the nodal agency.
3.Startups eligible under the scheme are defined as per the DPIIT notification of 19 February 2019.
True. Startups follow the DPIIT notification of 19 February 2019.
4.The Chips to Startup (C2S) Programme aims to generate industry-ready manpower in semiconductor chip design at B.Tech, M.Tech and PhD levels.
True. C2S is a capacity-building programme for chip design manpower.
Written by us from the release, not by UPSC; checked by a second model.
Worth revising until Prelims 2027: most news questions come within two years of the event.