- Why in news
- On 18 September 2026, MeitY reported Day 2 of SEMICON India 2026 at Yashobhoomi, New Delhi. Minister Ashwini Vaishnaw set out the six pillars of ISM 2.0 and said ISM 1.0 met its goals in four years instead of six.
- What it is
- The India Semiconductor Mission (ISM) is the programme under MeitY to build a domestic chip ecosystem. ISM 1.0 began in 2021 and backed fabs, ATMP/OSAT units and chip design. ISM 2.0 is the next phase and widens support to materials, machines, research and talent.
- Six pillars of ISM 2.0
- Design; Machines and Materials; more fabs; ATMP/OSAT industry; R&D; and Talent Development.
- ISM 1.0 timeline
- Planned as a six-year programme, it met its objectives in four years.
- Plants under ISM 1.0
- Twelve plants were approved under ISM 1.0, and five have started commercial production.
- Expected design companies
- The Minister estimated at least 200 chip design companies would emerge under ISM 2.0.
- Nodal ministry
- ISM sits under the Ministry of Electronics and Information Technology.
- Approval and outlay
- The Union Cabinet approved Semicon 2.0 on 15 July 2026 with an outlay of Rs 1,27,500 crore.
- Semicon 1.0 outlay
- Semicon 1.0 was approved in December 2021 with an outlay of Rs 76,000 crore.
- Semicon 1.0 units
- Twelve units were approved: one silicon fab, one silicon carbide fab, one GaN Micro LED display fab and nine ATMP/OSAT units. Five have begun commercial production.
- Concentration of production
- Taiwan produces over 60% of global chips and nearly 90% of advanced chips.
- Six pillars
- Design; Machines and Materials; more Fabs; ATMP/OSAT; R&D; Talent Development.
- Nodal agency
- ISM invites applications, appraises them, recommends applicants and oversees implementation.
- C-DAC role
- ISM may implement the design and deployment categories with C-DAC's help.
- Duration
- Projects generally run up to six years. Applications stay open initially for three years.
- Funding and review
- MeitY makes budget provisions; a mid-term assessment follows three years of implementation.
- Design incentive
- Pillar 1 includes a Deployment-Linked Incentive (DLI) for chips, IPs and SoCs.
- Outlay
- Semicon 2.0 has a total budget outlay of Rs.1,27,500 crore.
- ISM 1.0 manufacturing
- Twelve manufacturing units were approved with over Rs.1.64 lakh crore investment: one silicon fab, one SiC fab, one GaN Micro LED display fab and nine packaging units.
- Commercial production
- Micron, Kaynes and CG Semi have started commercial production.
- Projects approved
- Two new projects, both in Gujarat, were cleared. One is a compound semiconductor fab with ATMP at Dholera; the other is an OSAT unit at Surat.
- Crystal Matrix Limited, Dholera
- It will make Mini/Micro-LED display modules and offer GaN foundry services, including epitaxy on 6-inch wafers.
- Suchi Semicon, Surat
- An OSAT facility for discrete semiconductors, with capacity of 1033.20 million chips a year.
- ISM tally
- Approved projects under ISM now total 12, with cumulative investment of about Rs 1.64 lakh crore.
- Design support
- Government design infrastructure support covers 315 academic institutions and 104 start-ups.
- OSAT meaning
- OSAT stands for Outsourced Semiconductor Assembly and Test: firms that package and test chips made by fabs.
- Talent target
- The 10-year target is to train 85,000 engineers in semiconductor design, and the minister says good progress was made in four years.
- EDA tool access
- EDA tools backed by firms such as Synopsys, Cadence and Siemens are available in 315 academic institutions.
- Fabrication of student chips
- Student-designed chips are fabricated and tested at the Semiconductor Laboratory (SCL), Mohali.
- Expansion under Semicon 2.0
- The programme will grow from 315 to 500 universities.
- EDA tools
- 350 universities have been given access to EDA tools, used by 65 thousand engineers.
- ISM 2.0 aims
- It targets production of equipment and materials, design of full-stack Indian IP, and stronger supply chains.
Don’t confuse with Fab vs fabless: A fab makes chips on wafers. A fabless firm only designs chips and uses a foundry to make them.
Don’t confuse with ATMP vs OSAT: ATMP is Assembly, Testing, Marking and Packaging; OSAT is Outsourced Semiconductor Assembly and Test. Both handle the post-fabrication stage.
Don’t confuse with Fab vs ATMP/OSAT: A fab makes the chip on wafers; ATMP/OSAT packages and tests the finished chip.
Don’t confuse with ISM 1.0 vs Semicon 2.0: ISM 1.0 (2021) backed fabs, packaging and design. Semicon 2.0 adds machines, materials, advanced R&D and deeper talent building.
Don’t confuse with Compound vs silicon semiconductors: Compound semiconductors like GaN combine elements and suit power, RF and optoelectronics. Silicon is a single-element material used in most logic chips.
Don’t confuse with ISM vs SCL Mohali: ISM is the national programme under MeitY. SCL Mohali is a government fab laboratory used to make the student chips.
Don’t confuse with C2S vs fab incentives: C2S is about design talent and startups. Fab and ATMP/OSAT subsidies are separate parts of ISM.
Don’t confuse with EDA tools vs tapeout: EDA tools are software used to design chips. Tapeout is the final design submission for fabrication.
Don’t confuse with ISM vs ECMS: ISM backs chip fabs, packaging, design, equipment and materials. ECMS supports electronic components and sub-assemblies manufacturing.
Don’t confuse with ISM vs PLI for electronics: ISM is a semiconductor-specific mission. PLI schemes give production-linked incentives on sales across electronics products.
Schemes: 52 Prelims questions since 2013, 10 in Prelims 2026 alone. They test features, the period and who funds it. In Mains, 33 news-triggered questions, mostly GS3.
Why it matters
- Support across the whole value chain can cut import dependence and build strategic resilience in chips.
- Design strength and talent can move India from design services to owning chip IP and products.
- Cuts import dependence, as India spent about USD 150 billion on chip imports in FY17-FY25.
- Builds the full value chain and supports supply chain resilience and strategic autonomy.
- Creates high-value jobs and supports strategic sectors such as space and defence.
- Strengthens supply-chain resilience and national security in a critical technology.
- Covers the full value chain, including equipment, materials and talent, not just fabs.
- Can create 50,000-60,000 direct jobs, according to the Minister.
- Cuts import dependence and strengthens supply chain resilience and national security.
- Builds upstream capacity in materials, machines and design IP, not just assembly.
- Supports growth across sectors such as automobiles, telecom, electronics and aerospace.
- Adds compound semiconductor and display capability, reducing import dependence in a strategic technology.
- Creates skilled jobs and builds a Gujarat cluster at Dholera and Surat.
- Builds a skilled design workforce, which is a key gap in India's chip ecosystem.
- Open-access EDA tools lower cost for students and startups across the country.
- Reduces import dependence in a strategic input for electronics, defence and autos.
- Builds jobs and a full chain from design to packaging, and spreads units across states.
- Reduces import dependence in chips and strengthens supply chains.
- Equipment, materials and IP move India beyond assembly into deeper value chains.
Problems
- Fabs need heavy capital, steady power and ultra-pure water, and depend on imported machines and materials.
- Only five of twelve approved plants are producing, and the talent trained is below the design target of 85,000.
- Chip manufacturing is highly complex, capital-intensive and needs long, steady policy support.
- Production is concentrated in a few economies, so India depends on trusted partners for tools and technology.
- Only five of twelve approved units were producing by 2026, so execution and talent remain gaps.
- Chip fabs need very large capital, water, power and skilled staff.
- India depends on imported equipment and materials, and global competition for subsidies is heavy.
- Projects take years to deliver, and fiscal support is large.
- Fabs need huge capital, water, power and ultra-pure inputs, with long gestation.
- India's current nodes (28nm-110nm) lag leading-edge global technology.
- Dependence on foreign technology partners and a shortage of skilled engineers.
- Chip fabs need heavy capital, water, power and skilled workers, and face global competition.
- Dependence on imported materials, equipment and technology persists.
- Trained designers may leave for foreign firms, so retention is a risk.
- Training must be matched by fabs and industry jobs to be useful.
- Fabs need large capital, water, power and scarce skilled talent.
- Most approved projects are packaging, and India depends on foreign technology partners.
- Fabs need heavy capital, water, power and a mature supplier base.
- Shortage of skilled chip designers and process engineers.
Way forward
- Localise materials and equipment and keep strong partnerships with trusted countries.
- Link research, industry and academia so design talent leads to products and IP.
- Sustain long-term funding and speed up approvals and execution of approved units.
- Build the machines, materials and talent base while deepening trusted international partnerships.
- Link R&D to industry so design work grows into products made in India.
- Build equipment and materials suppliers alongside fabs.
- Link talent training to industry needs and speed up approvals.
- Use the mid-term review to correct design and funding gaps.
- Develop advanced nodes through R&D tie-ups with leading centres in India and abroad.
- Build supplier clusters for gases, chemicals and equipment alongside fabs.
- Align training in universities with industry needs such as clean room and fab skills.
- Build the supply chain of materials, gases and equipment through ISM 2.0.
- Link design, talent and manufacturing so projects reach commercial scale.
- Link academic training with industry internships and local fabs.
- Support design startups to turn student chips into products.
- Build materials, equipment and talent base, as ISM 2.0 intends.
- Speed up project execution and anchor demand through domestic chip design.
- Build industry-linked research and training centres with steady funding.
- Develop local equipment and materials clusters alongside fabs.
Put in your answer
ISM 1.0 execution record: Five of twelve approved plants are in commercial production, and the first phase ended ahead of schedule.
Semicon 1.0 progress: Twelve units approved with over Rs 1.64 lakh crore investment; five are producing.
Design talent: India employs nearly 20% of the global chip design workforce.
Talent target: India reached its target of 85,000 semiconductor engineers in four years against a 10-year plan; a further one lakh is targeted.
Design by students: Students from Tier-II and Tier-III cities have designed more than 250 chips.
Market share: Close to 10% of the global semiconductor market is expected to be in India in the coming years.
ISM 1.0 investment: Twelve approved manufacturing units carry over Rs.1.64 lakh crore of investment.
Design ecosystem: 24 design projects approved for support; 105 start-ups/MSMEs given EDA tool access.
Talent pipeline: About 68,000 students trained on EDA tools across 315 universities.
ISM scale: 12 approved projects with about Rs 1.64 lakh crore investment show the mission's progress.
Execution status: Two projects have begun commercial shipments from India, and two more are expected to follow soon.
EDA programme scale: Over 1.85 crore hours of EDA tool use recorded; called the world's largest open-access EDA programme.
Jobs demand: As the global industry reaches USD 2 trillion, about 2 million skilled professionals will be needed.
Investment scale: 10 approved projects carry about Rs 1.6 lakh crore of envisaged investment.
ECMS: ECMS has drawn investment commitments at double its target, with outlay now proposed at Rs 40,000 crore.
- 2025Mains GS3 · Q16Challenges facing India's semiconductor industry and salient features of ISM
- 2025Mains GS3 · Q12Rationale, achievements and improvements of the PLI manufacturing incentive scheme
- 2024Mains GS2 · Q9West fostering India as alternative to China's supply chain, with examples.
- 2026Prelims Q83Which semiconductor plant and location pair is incorrectly matched in India?
UPSC’s own questions that come close to this issue, from our Prelims and Mains banks.
Prelims practice · Single answer
Ours, not from a UPSC paper
With reference to India's semiconductor programme, as explained by PIB on 17 September 2026, consider the following statements: 1. Semicon 2.0 was approved by the Union Cabinet in July 2026 with an outlay of Rs 1,27,500 crore. 2. Semicon 1.0 was approved in December 2021 with an outlay larger than that of Semicon 2.0. 3. The Design Linked Incentive Scheme was introduced under Semicon 2.0 to support chip design. 4. The Semiconductor Laboratory, which develops flight-grade chips for satellites and launch vehicles, is located in Mohali. Which of the statements given above are correct?
Which of the statements given above are correct?
True or false?
1 of 19
Statements the way Prelims prints them. Say first, then see the fact.
1.Semicon 2.0 was approved by the Union Cabinet in July 2026 with an outlay of Rs 1,27,500 crore.
True. Approved 15 July 2026, outlay Rs 1,27,500 crore.
2.The Semiconductor Laboratory (SCL), which develops flight-grade chips for satellites and launch vehicles, is located in Mohali.
True. SCL is in Mohali, Punjab.
3.Silicon, the most widely used semiconductor material, is obtained from silica found in sand.
True. Silicon comes from silica.
4.The India Semiconductor Mission is the nodal agency for Semicon 2.0.
True. ISM is the nodal agency; it appraises applications and oversees implementation.
5.ISM may implement the design and deployment categories with the assistance of the Centre for Development of Advanced Computing.
True. C-DAC may assist ISM in the design and deployment categories.
6.Semicon 2.0 will initially accept applications for ten years.
False. It will initially remain open for applications for three years.
7.The scheme's mid-term assessment will be conducted after five years of implementation.
False. The mid-term assessment comes after three years, or as required.
8.Semicon 2.0 has a total budget outlay of Rs.1,27,500 crore.
True. The outlay is Rs.1,27,500 crore.
9.The India Semiconductor Mission functions under the Ministry of Electronics and Information Technology.
True. ISM is under MeitY.
10.The Semicon India Programme has a total outlay of Rs 76,000 crore.
True. The outlay is Rs 76,000 crore.
11.Of the 10 projects approved under the programme, 8 are fabs and 2 are packaging units.
False. 2 are fabs and 8 are packaging units.
12.The India Semiconductor Mission is the nodal agency for appraisal and recommendation of semiconductor projects under the programme.
True. ISM is the nodal agency for appraisal and recommendations.
13.The Tata Electronics fab in Gujarat is being set up in technology partnership with a company from South Korea.
False. The partner is PSMC, Taiwan.
14.The Micron facility in Gujarat is meant for assembly and test of both DRAM and NAND products.
True. Micron's Gujarat unit does assembly and test for DRAM and NAND.
15.The India Semiconductor Mission functions under the Ministry of Commerce and Industry.
False. ISM is under the Ministry of Electronics and IT (MeitY).
16.ISM 2.0 is meant to produce equipment and materials and design full-stack Indian IP.
True. These are stated aims of ISM 2.0.
17.The Electronics Components Manufacturing Scheme was launched in April 2025.
True. ECMS was launched in April 2025.
18.The ECMS outlay is proposed to be increased to Rs 40,000 crore.
True. The proposed outlay is Rs 40,000 crore.
19.The India Semiconductor Mission is an independent body set up by an Act of Parliament.
False. It is a programme, a division within the Digital India Corporation, not a statutory body.
Written by us from the release, not by UPSC; checked by a second model.
Mains practice
15 marks · 250 words
India's Cabinet has approved Semicon 2.0 with an outlay of Rs 1,27,500 crore, extending support from fabs and ATMP/OSAT units to materials, machines, design, research and talent. Examine the provisions of the scheme and discuss the challenges India faces in building a complete domestic semiconductor value chain.
Worth revising until Prelims 2028: most news questions come within two years of the event.